Power Side-channel Leakage and Its Countermeasure in the High-Level Synthesis based Design Flow

Prof. Yuko Hara-Azumi, Tokyo Institute of Technology

November 28th at 2:30am, Room S.U.A5 lab

Abstract : Application-dedicated hardware designs are a promising solution to improve power and energy efficiency, which is particularly important in the Internet of Things (IoT) era. However, such hardware designs may have side channels (e.g., power side channel) that can be leveraged to analyze data (or computations) being processed. In this seminar, I will first briefly explain the power side-channel attack mechanism and countermeasures against the attack. Then, I will introduce the high-level synthesis (HLS) based hardware design flow, which is currently used for various application designs but is not security aware yet. In our recent work that was published at ACM Trans. on Embedded Computing Systems, we integrated side-channel security (on a basis of a provably countermeasure called the threshold implementation) into the state-of-the-art high-level-synthesis-based hardware design flow. I will demonstrate that our proposed method can successfully improve the side-channel security in our case studies for lightweight block ciphers that are suitable for resource-constrained IoT edges.

Bio : Yuko Hara-Azumi received her Ph.D. degree in Information Science from Nagoya University, Japan, in 2010. She was a JSPS postdoctoral research fellow from 2010 to 2012, during which she was also a visiting scholar at University of California, Irvine, USA and Karlsruhe Institute of Technology, Germany. In 2012, she joined Nara Institute of Science and Technology, as an assistant professor. Since 2014, she has been with the School of Engineering, Tokyo Institute of Technology, where she is currently an associate professor. She was a visiting scholar at KU Leuven, Belgium in 2023. Her research interests include system-level design automation, microprocessor architecture, and hardware/software co-design for embedded/IoT systems.